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september 2010 doc id 16891 rev 19 1/40 1 m24c64-w m24c64-r m24c64-f 64 kbit serial i2c bus eeprom features compatible with all i 2 c bus modes: ? 1 mhz fast-mode plus ? 400 khz fast mode ? 100 khz standard mode memory array: ? 64 kb (8 kbytes) of eeprom ? page size: 32 bytes write ? byte write within 5 ms ? page write within 5 ms random and sequential read modes write protect of the whole memory array single supply voltage: ? m24c64-w: 2.5 v to 5.5 v ? m24c64-r: 1.8 v to 5.5 v ? m24c64-f: 1.7 v to 5.5 v enhanced esd/latch-up protection more than 1 million write cycles more than 40-year data retention packages ? so8, tssop8, ufdfpn8 packages: ecopack2? (rohs-compliant and halogen-free) ? pdip8 package: ecopack1? (rohs- compliant) pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mb) 2 3 mm (mlp) www.st.com
contents m24c64-w, m24c64-r, m24c64-f 2/40 doc id 16891 rev 19 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 18 4.10 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.11 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m24c64-w, m24c64-r, m24c64-f contents doc id 16891 rev 19 3/40 5 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables m24c64-w, m24c64-r, m24c64-f 4/40 doc id 16891 rev 19 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. operating conditions (m24xxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 8. operating conditions (m24xxx-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. operating conditions (m24xxx-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. dc characteristics (m24xxx-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. dc characteristics (m24xxx-w - device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. dc characteristics (m24xxx-r - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. dc characteristics (m24xxx-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 30 table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. tssop8 ? 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 table 21. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 23. available m24c64 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
m24c64-w, m24c64-r, m24c64-f list of figures doc id 16891 rev 19 5/40 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. dip, so, tssop and ufdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) 10 figure 5. i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus )10 figure 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 13. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 30 figure 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 31 figure 16. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
description m24c64-w, m24c64-r, m24c64-f 6/40 doc id 16891 rev 19 1 description the m24c64-w, m24c64-r and m24c64-f devices are i 2 c-compatible electrically erasable programmable memories (eeprom ). they are organized as 8192 8 bits. figure 1. logic diagram i 2 c uses a two-wire serial interface, comprising a bidirectional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 2 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. !)f % % 3$! 6 ## -xxx 7# 3#, 6 33
m24c64-w, m24c64-r, m24c64-f description doc id 16891 rev 19 7/40 figure 2. dip, so, tssop and ufdfpn connections 1. see package mechanical data section for package dimensions, and how to identify pin-1. table 1. signal names signal name function direction e0, e1, e2 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage v ss ground 3$! 6 33 3#, 7# % % 6 ## % !)f
signal description m24c64-w, m24c64-r, m24c64-f 8/40 doc id 16891 rev 19 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code as shown in figure 3 . when not connected (left floating), these inputs are read as low (0,0,0). figure 3. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, th e signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24c64-w, m24c64-r, m24c64-f signal description doc id 16891 rev 19 9/40 2.5 v ss ground v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 7 , ta bl e 8 and ta bl e 9 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in ta bl e 7 , ta bl e 8 and ta b l e 9 . the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 8 and ta b l e 9 ). until v cc passes over the por threshold, the device is reset and in standby power mode. in a similar way, during power-down (continuous decay of v cc ), as soon as v cc drops below the por threshold voltage, the device is reset and stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decay of v cc ), the device must be in standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
signal description m24c64-w, m24c64-r, m24c64-f 10/40 doc id 16891 rev 19 figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) figure 5. i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) 1 10 100 10 100 1000 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) when t low = 1. 3 s (min v a l u e for f c = 400 khz), the r bus c bus time con s t a nt m us t b e b elow the 400 n s time con s t a nt line repre s ented on the left. i2c bus m as ter m24xxx r bus v cc c bus s cl s da a i14796 b r bus c bus = 400 n s here r bus c bus = 120 n s 4 k 3 0 pf 1 10 100 10 100 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) a i14795d i2c bus m as ter m24xxx r bus v cc c bus s cl s da r bus c bus = 270 n s when t low = 700 n s (m a x po ss i b le v a l u e for f c = 1 mhz), the r bus c bus time con s t a nt m us t b e b elow the 270 n s time con s t a nt line repre s ented on the left. when t low = 400 n s (min v a l u e for f c = 1 mhz), the r bus c bus time con s t a nt m us t b e b elow the 100 n s time con s t a nt line repre s ented on the left. here, r bus c bus = 150 n s r bus c bus = 100 n s 5 3 0
m24c64-w, m24c64-r, m24c64-f signal description doc id 16891 rev 19 11/40 figure 6. i 2 c bus protocol table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1010e2e1e0rw table 3. address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 table 4. address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
memory organization m24c64-w, m24c64-r, m24c64-f 12/40 doc id 16891 rev 19 3 memory organization the memory is organized as shown in figure 7 . figure 7. block diagram ai06899 wc e1 e0 control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder scl sda e2
m24c64-w, m24c64-r, m24c64-f device operation doc id 16891 rev 19 13/40 4 device operation the device supports the i 2 c protocol. this is summarized in figure 6 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 4.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write command triggers the internal write cycle. 4.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 4.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
device operation m24c64-w, m24c64-r, m24c64-f 14/40 doc id 16891 rev 19 4.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. table 5. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x ? 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il ?? 32 start, device select, rw = 0
m24c64-w, m24c64-r, m24c64-f device operation doc id 16891 rev 19 15/40 figure 8. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev select byte address byte address data in wc start page write dev select byte address byte address data in 1 wc data in 2 ai01120d page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
device operation m24c64-w, m24c64-r, m24c64-f 16/40 doc id 16891 rev 19 4.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 9 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a period of time from the start condition until the end of the two address byte s) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 8 . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( ta b l e 3 ) is sent first, followed by the least significant byte ( ta bl e 4 ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. 4.7 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 9 . 4.8 page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b12- b5) are the same. if more bytes ar e sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (inside the page) is incremented. the transfer is terminated by the bus master generating a stop condition.
m24c64-w, m24c64-r, m24c64-f device operation doc id 16891 rev 19 17/40 figure 9. write mode sequences with wc = 0 (data write enabled) stop start byte write dev select byte address byte address data in wc start page write dev select byte address byte address data in 1 wc data in 2 ai01106d page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
device operation m24c64-w, m24c64-r, m24c64-f 18/40 doc id 16891 rev 19 figure 10. write cycle polling flowchart using ack 4.9 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ta b l e 1 6 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 10 , is: 1. initial condition: a write cycle is in progress. 2. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). 3. step 2: if the device is busy with the in ternal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847d next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
m24c64-w, m24c64-r, m24c64-f device operation doc id 16891 rev 19 19/40 figure 11. read mode sequences 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 4 th bytes) must be identical. start dev select * byte address byte address start dev select data out 1 ai01105d data out n stop start current address read dev select data out random address read stop start dev select * data out sequential current read stop data out n start dev select * byte address byte address sequential random read start dev select * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
device operation m24c64-w, m24c64-r, m24c64-f 20/40 doc id 16891 rev 19 4.10 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. 4.11 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 11 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 4.12 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 11 , without acknowledging the byte. 4.13 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 11 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 4.14 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode.
m24c64-w, m24c64-r, m24c64-f initial delivery state doc id 16891 rev 19 21/40 5 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 6 maximum rating stressing the device outside the ratings listed in ta bl e 6 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit ambient operating temperatur e with power applied ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020d (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v i ol dc output current (sda = 0) - 5 ma v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114, c1=100pf, r1=1500 ? , r2=500 ? ) ?3000 3000 v
dc and ac parameters m24c64-w, m24c64-r, m24c64-f 22/40 doc id 16891 rev 19 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 12. ac test measurement i/o waveform table 7. operating conditions (m24xxx-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperatur e (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 8. operating conditions (m24xxx-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 9. operating conditions (m24xxx-f) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c table 10. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m24c64-w, m24c64-r, m24c64-f dc and ac parameters doc id 16891 rev 19 23/40 table 11. input parameters symbol parameter (1) 1. characterized value, not tested in production. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l (2) 2. e2,e1,e0: input impedance when the memory is selected (after a start condition). input impedance (e2, e1, e0, wc) v in < 0.3v cc 30 k ? z h (2) input impedance (e2, e1, e0, wc) v in > 0.7v cc 500 k ? table 12. dc characteristics (m24xxx-w, device grade 6) symbol parameter test conditions (see table 7 and table 10 ) min. max. unit i li input leakage current (scl, sda, e0, e1, e2) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) 2.5 v < v cc < 5.5 v, f c = 400 khz (rise/fall time < 50 ns) 2ma 2.5 v < v cc < 5.5 v, f c = 1 mhz (1) (rise/fall time < 50 ns) 1. only for devices operating at f c max = 1 mhz (see table 17 ) 2.5 ma i cc0 supply current (write) during t w , 2.5 v < v cc < 5.5 v 5 (2) 2. characterized value, not tested in production. ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 2.5 v 3. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 2a device not selected (3) , v in = v ss or v cc , v cc = 5.5 v 5 (4) 4. the new m24c64-w devices (identified by the process letter k) offer i cc1 = 3a (max) a v il input low voltage (scl, sda, wc) ?0.45 0.3v cc v v ih input high voltage (scl, sda) 0.7v cc 6.5 v input high voltage (wc, e0, e1, e2) 0.7v cc v cc +0.6 v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v 0.4 v
dc and ac parameters m24c64-w, m24c64-r, m24c64-f 24/40 doc id 16891 rev 19 table 13. dc characteristics (m24xxx-w - device grade 3) symbo l parameter test conditions (in addition to those in table 7 and table 10 ) min. max. unit i li input leakage current (scl, sda, e0, e1, e2) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) f c = 400 khz 2 ma i cc0 supply current (write) during t w 5 (1) 1. characterized value, not tested in production. ma i cc1 standby supply current device not selected (2) , v in = v ss or v cc 2. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 10 a v il input low voltage (scl, sda, wc) ?0.45 0.3v cc v v ih input high voltage (scl, sda) 0.7v cc 6.5 v input high voltage (wc, e0, e1, e2) 0.7v cc v cc +0.6 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v 0.4 v
m24c64-w, m24c64-r, m24c64-f dc and ac parameters doc id 16891 rev 19 25/40 table 14. dc characteristics (m24xxx-r - device grade 6) symbol parameter test conditions (in addition to those in table 8 and table 10 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.8 v, f c = 400 khz 0.8 (1) 1. the new m24c64 device (identified by the process letter k) offers i cc =1.5ma. ma f c = 1 mhz (2) 2. only for devices operating at f c max = 1 mhz (see table 17 ). 2.5 ma i cc0 supply current (write) during t w , 1.8 v < v cc < 2.5 v 3 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.8 v 4. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 1a v il input low voltage (scl, sda, wc) 1.8 v ? v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) 1.8 v ? v cc < 2.5 v 0.75v cc 6.5 v input high voltage (wc, e0, e1, e2) 1.8 v ? v cc < 2.5 v 0.75v cc v cc +0.6 v v ol output low voltage i ol = 1 ma, v cc = 1.8 v 0.2 v
dc and ac parameters m24c64-w, m24c64-r, m24c64-f 26/40 doc id 16891 rev 19 table 15. dc characteristics (m24xxx-f) symbol parameter test conditions (in addition to those in table 9 and table 10 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.7 v, f c = 400 khz 0.8 (1) 1. the new m24c64 device (identified by the process letter k) offers i cc =1.5ma. ma f c = 1 mhz (2) 2. only for devices operating at f c max = 1 mhz (see table 17 ). 2.5 ma i cc0 supply current (write) during t w , 1.7 v < v cc < 2.5 v 3 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.7 v 4. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 1a v il input low voltage (scl, sda, wc) 1.7 v ? v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) 1.7 v ? v cc < 2.5 v 0.75v cc 6.5 v input high voltage (wc, e0, e1, e2) 1.7 v ? v cc < 2.5 v 0.75v cc v cc +0.6 v v ol output low voltage i ol = 1 ma, v cc = 1.7 v 0.2 v
m24c64-w, m24c64-r, m24c64-f dc and ac parameters doc id 16891 rev 19 27/40 table 16. 400 khz ac characteristics test conditions (in ad dition to those in table 7 , table 8 , table 9 and table 10 ) symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 120 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 100 (4) 4. the new m24c64 device (identified by the process letter k) offers t clqx = 100 ns (min) and t clqv = 100 ns (min), while the current device offers t clqx = 200 ns (min) and t clqv = 200 ns (min). both series offer a safe margin compared to the i 2 c specification which recommends t clqv = 0 ns (min). ns t clqv (5)(6) 5. to avoid spurious start and st op conditions, a minimum delay is pl aced between scl=1 and the falling or rising edge of sda. 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is within the values specified in figure 4 . t aa clock low to next data valid (access time) 100 (4) 900 ns t chdl t su:sta start condition setup time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 ms t ns pulse width ignored (input filter on scl and sda) - single glitch 80 (7) 7. the current m24c64 device offers t ns =100 ns (min), the new m24c64 device (identified by the process letter k) offers t ns =80 ns (min). both products offer a safe margin compared to the 50 ns minimum value recommended by the i 2 c specification. ns
dc and ac parameters m24c64-w, m24c64-r, m24c64-f 28/40 doc id 16891 rev 19 table 17. 1 mhz ac characteristics (1) 1. preliminary information, only new m 24c64 devices identified by the proc ess letter k are qualified at 1 mhz. test conditions specified in table 7 , table 8 and table 10 symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz, or less than 120 ns when f c <1mhz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t ql1ql2 (6) t f sda (out) fall time 20 (3) 3. with c l = 10 pf 120 ns t dxcx t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx t dh data out hold time 100 - ns t clqv (4)(5) 4. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. 5. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time consta nt is within the values specified in figure 5 . t aa clock low to next data valid (access time) 100 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t w t wr write time - 5 ms t ns (6) 6. characterized only, not tested in production. pulse width ignored (input filter on scl and sda) -80ns
m24c64-w, m24c64-r, m24c64-f dc and ac parameters doc id 16891 rev 19 29/40 figure 13. ac waveforms 3#, 3$!)n 3#, 3$!/ut 3#, 3$!)n t#(#, t$,#, t#($, 3tart condition t#,#( t$8#( t#,$8 3$! )nput 3$! #hange t#($( t$($, 3top condition $atavalid t#,16 t#,18 t#($( 3top condition t#($, 3tart condition 7ritecycle t7 !)f 3tart condition t#(#, t8(8( t8(8( t8,8, t8,8, $atavalid t1,1,
package mechanical data m24c64-w, m24c64-r, m24c64-f 30/40 doc id 16891 rev 19 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package outline 1. drawing is not to scale. table 18. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 5.33 0.2098 a1 0.38 0.0150 a2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.20 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.3650 0.3551 0.4000 e 7.87 7.62 8.26 0.3098 0.3000 0.3252 e1 6.35 6.10 7.11 0.2500 0.2402 0.2799 e2.54? ?0.1000? ? ea 7.62 ? ? 0.3000 ? ? eb 10.92 0.4299 l 3.30 2.92 3.81 0.1299 0.1150 0.1500 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
m24c64-w, m24c64-r, m24c64-f package mechanical data doc id 16891 rev 19 31/40 figure 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.75 0.0689 a1 0.10 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.28 0.48 0.0110 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.10 0.0039 d 4.90 4.80 5.00 0.1929 0.1890 0.1969 e 6.00 5.80 6.20 0.2362 0.2283 0.2441 e1 3.90 3.80 4.00 0.1535 0.1496 0.1575 e1.27? ?0.0500? ? h 0.25 0.50 k 08 08 l 0.40 1.27 0.0157 0.0500 l1 1.04 0.0410 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data m24c64-w, m24c64-r, m24c64-f 32/40 doc id 16891 rev 19 figure 16. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 20. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 ? 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
m24c64-w, m24c64-r, m24c64-f package mechanical data doc id 16891 rev 19 33/40 figure 17. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline 1. drawing is not to scale. 2. the central pad (the e2 d2 area in the above illustration) is internally pulled to v ss . it should not be connected to any other voltage or signal line on the pcb, for example during the soldering process. table 21. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.55 0.50 0.60 0.0217 0.0197 0.0236 a1 0.02 0.00 0.05 0.0008 0 0.0020 b 0.25 0.20 0.30 0.0098 0.0079 0.0118 d 2.00 1.90 2.10 0.0787 0.0748 0.0827 d2 1.60 1.50 1.70 0.0630 0.0591 0.0669 ddd 0.08 0.0031 e 3.00 2.90 3.10 0.1181 0.1142 0.1220 e2 0.20 0.10 0.30 0.0079 0.0039 0.0118 e0.50? ?0.0197? ? l 0.45 0.40 0.50 0.0177 0.0157 0.0197 l1 0.15 0.0059 l3 0.30 0.0118 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
part numbering m24c64-w, m24c64-r, m24c64-f 34/40 doc id 16891 rev 19 9 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 22. ordering information scheme example: m24c64? w mn 6 t p /p device type m24 = i 2 c serial access eeprom device function c64? = 64 kbit (8192 x 8) operating voltage w = v cc = 2.5 v to 5.5 v r = v cc = 1.8 v to 5.5 v f = v cc = 1.7 v to 5.5 v package bn = pdip8 (1) 1. ecopack1 ? (rohs-compliant). mn = so8 (150 mil width) (2) 2. ecopack2 ? (rohs-compliant and halogen-free). dw = tssop8 (169 mil width) (2) mb = ufdfpn8 (mlp8) (2) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c 5 = consumer: device tested with standard test flow over ?20 to 85c option blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant) process (3) 3. used only for device gr ade 3 and wlcsp packages. p = f6dp26% chartered a = f8l rousset (only for the wlcsp package)
m24c64-w, m24c64-r, m24c64-f part numbering doc id 16891 rev 19 35/40 table 23. available m24c64 products (package, voltage range, temperature grade) package m24c64-f 1.7 v to 5.5 v m24c64-r 1.8 v to 5.5 v m24c64-w 2.5 v to 5.5 v dip8 (bn) - - grade6 so8n (mn) - grade 6 grade 3 grade 6 tssop8 (dw) grade 5 grade 6 grade 6 mlp8 (mb) grade 6 - -
revision history m24c64-w, m24c64-r, m24c64-f 36/40 doc id 16891 rev 19 10 revision history table 24. document revision history date revision changes 22-dec-1999 2.3 tssop8 package in place of tssop14 (pp 1, 2, orderinginfo, packagemechdata). 28-jun-2000 2.4 tssop8 package data corrected 31-oct-2000 2.5 references to temperature range 3 removed from ordering information voltage range -s added, and range -r removed from text and tables throughout. 20-apr-2001 2.6 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated references to psdip changed to pdip and package mechanical data updated 16-jan-2002 2.7 test condition for i li made more precise, and value of i li for e2-e0 and wc added -r voltage range added 02-aug-2002 2.8 document reformatted using new template. tssop8 (3x3mm2 body size) package (msop8) added. 5ms write time offered for 5v and 2.5v devices 04-feb-2003 2.9 so8w package removed. -s voltage range removed 27-may-2003 2.10 tssop8 (3x3mm2 body size) package (msop8) removed 22-oct-2003 3.0 table of contents, and pb-free options added. minor wording changes in summary description, power-on reset, memory addressing, write operations, read operations. v il (min) improved to -0.45v. 01-jun-2004 4.0 absolute maximum ratings for v io (min) and v cc (min) improved. soldering temperature information clarified for rohs compliant devices. device grade clarified 04-nov-2004 5.0 product list summary table added. device grade 3 added. 4.5-5.5v range is not for new design. some minor wording changes. aec-q100- 002 compliance. t ns (max) changed. v il (min) is the same on all input pins of the device. z wcl changed. 05-jan-2005 6.0 ufdfpn8 package added. small text changes.
m24c64-w, m24c64-r, m24c64-f revision history doc id 16891 rev 19 37/40 29-jun-2006 7 document converted to new st template. m24c32 and m24c64 products (4.5 to 5.5v supply voltage) removed. m24c64 and m24c32 products (1.7 to 5.5v supply voltage) added. section 2.3: chip enable (e0, e1, e2) and section 2.4: write control (wc) modified, section 2.6: supply voltage (vcc) added and replaces power on reset: vcc lock-out write protect section. t a added, note 1 updated and t lead specified for pdip packages in table 6: absolute maximum ratings . i cc0 added, i cc voltage conditions changed and i cc1 specified over the whole voltage range in table 24: dc characteristics (m24xxx-w, device grade 6) . i cc0 added, i cc frequency conditions changed and i cc1 specified over the whole voltage range in table 26: dc characteristics (m24xxx-r - device grade 6) . t w modified in table 28: ac characteristics . so8n package specifications updated (see figure 15 and ta bl e 1 9 ). device grade 5 added, b and p process letters added to ta b l e 2 2 : ordering information scheme . small text changes. 03-jul-2006 8 i cc1 modified in table 24: dc characteristics (m24xxx-w, device grade 6) . note 1 added to table 27: dc characteristics (m24xxx-f) and table title modified. 17-oct-2006 9 ufdfpn8 package specif ications updated (see ta bl e 2 1 ). m24128-bw- and m24128-br part numbers added. generic part number corrected in features on page 1 . i cc0 corrected in ta bl e 2 5 and ta bl e 2 4 . packages are ecopack? compliant. 27-apr-2007 10 available packages and temperature ranges by product specified in ta bl e 2 2 , ta bl e 2 4 and ta bl e 2 5 . notes modified below table 23: input parameters . v ih max modified in dc characteristics tables (see ta b l e 2 4 , ta b l e 2 5 , ta bl e 2 6 and ta bl e 2 7 ). c process code added to table 22: ordering information scheme . for m24xxx-r (1.8 v to 5.5 v range) products assembled from july 2007 on, t w will be 5 ms (see table 28: ac characteristics . 27-nov-2007 11 small text changes. section 2.5: vss ground and section 4.9: ecc (error correction code) and write cycling added. v il and v ih modified in table 26: dc characteristics (m24xxx-r - device grade 6) . jedec standard reference updated below table 6: absolute maximum ratings . package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see section 8: package mechanical data ). table 24. document revision history (continued) date revision changes
revision history m24c64-w, m24c64-r, m24c64-f 38/40 doc id 16891 rev 19 18-dec-2007 12 added section 2.6.2: power-up conditions , updated section 2.6.3: device reset , and section 2.6.4: power-down conditions in section 2.6: supply voltage (vcc) . updated figure 4: i2c fast mode (fc = 400 khz): maximum rbus value versus bus parasitic capacitance (cbus) . replace m24128 and m24c64 by m24128-bfmb6 and m24c64-fmb6, respectively, in section 4.9: ecc (error correction code) and write cycling . added temperature grade 6 in table 21: operating conditions (m24xxx- f) . updated test conditions for i lo and v lo in table 24: dc characteristics (m24xxx-w, device grade 6) , table 25: dc characteristics (m24xxx-w, device grade 3) , and table 26: dc characteristics (m24xxx-r - device grade 6) . test condition updated for i lo , and v ih and v il differentiate for 1.8 v ? v cc < 2.5 v and 2.5 v ? v cc < 5.5 v in table 27: dc characteristics (m24xxx-f) . updated table 28: ac characteristics , and table 17: ac characteristics (m24xxx-f) . updated figure 13: ac waveforms . added m24128-bf in table 25: available m24c32 products (package, voltage range, temperature grade) . process b removed from table 22: ordering information scheme . 30-may-2008 13 small text changes. c process option and blank plating technology option removed from table 22: ordering information scheme . 15-jul-2008 14 wlcsp package added (see figure 3: wlcsp connections (top view, marking side, with balls on the underside) and section 8: package mechanical data ). section 4.9: ecc (error correction code) and write cycling updated. 16-sep-2008 15 i ol added to table 6: absolute maximum ratings . table 24: available m24c32 products (package, voltage range, temperature grade) and table 25: available m24c32 products (package, voltage range, temperature grade) updated. 05-jan-2009 16 i2c modes supported specified in features on page 1 . note removed from table 27: dc characteristics (m24xxx-f) . small text changes. table 24. document revision history (continued) date revision changes
m24c64-w, m24c64-r, m24c64-f revision history doc id 16891 rev 19 39/40 10-dec-2009 17 32 and 128 kbit densities removed. ecopack status of packages specified on page 1 and in ta b l e 2 2 : ordering information scheme . section 2.6.2: power-up conditions updated. figure 4: i2c fast mode (fc = 400 khz): maximum rbus value versus bus parasitic capacitance (cbus) updated. ecc section removed. t ns modified in table 23: input parameters . i cc1 and v ih updated in table 24: dc characteristics (m24xxx-w, device grade 6) , table 25: dc characteristics (m24xxx-w, device grade 3) , table 26: dc characteristics (m24xxx-r - device grade 6) and ta bl e 2 7 : dc characteristics (m24xxx-f) . note added to table 26: dc characteristics (m24xxx-r - device grade 6) . table 28: ac characteristics modified. figure 13: ac waveforms modified. note added below figure 17: ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline . small text changes. 05-feb-2010 18 number of bytes changed for page write in table 5: operating modes . 15-sep-2010 19 updated tables (process letter k) under section 6 : ? ta b l e 6 : esd hbm passes 3000 v updated tables (process letter k) under section 7 : ? ta b l e 1 7 (1mhz ac) inserted, ? ta b l e 1 6 , ta bl e 1 7 : tclqv(min) = 100 ns ? ta b l e 1 6 , ta bl e 1 7 : tns = 80 ns table 24. document revision history (continued) date revision changes
m24c64-w, m24c64-r, m24c64-f 40/40 doc id 16891 rev 19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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